1. Field of the Invention
The present invention relates generally to insulator layers within integrated circuits. More particularly, the present invention relates to methods for controlling the etch profiles of apertures formed through multi-layer insulator layers within integrated circuits.
2. Description of the Related Art
Integrated circuits are formed from semiconductor substrates within and upon whose surfaces are formed resistors, transistors, diodes and other electrical circuit elements. The electrical circuit elements are connected internally and externally to the semiconductor substrate upon which they are formed through patterned conductor layers which are separated by insulator layers.
In the process of connecting and interconnecting patterned conductor layers and electrical circuit elements which are separated by blanket insulator layers within integrated circuits, it is common in the art to employ photo lithographic and etching methods in forming apertures through those blanket insulator layers. When the blanket insulator layers are single layer blanket insulator layers, the apertures formed through those single layer blanket insulator layers may typically be etched through a single etch method to form apertures with uniform void-free sidewall etch profiles.
It is quite common, however, within advanced integrated circuits that blanket insulator layers are formed from blanket multi-layer insulator layers rather than blanket single layer insulator layers. Thus, it is also quite common within advanced integrated circuits that blanket multi-layer insulator layers when etched through a single etch method will typically yield through those blanket multi-layer insulator layers apertures having irregular sidewall etch profiles which exhibit voids. A schematic cross-sectional diagram illustrating the irregular sidewall etch profile of an aperture etched through a blanket two-layer multi-layer insulator layer employing a single etch method is shown in FIG. 1.
Shown within FIG. 1 is a substrate layer 10 having an aperture formed through a blanket two-layer multi-layer insulator layer formed upon the substrate layer 10. The aperture is defined by a pair of patterned first insulator layers 12a and 12b which reside beneath a pair of patterned second insulator layers 14a and 14b. A pair of patterned photo resist layers 16a and 16b is employed as a mask in sequentially patterning the pair of patterned second insulator layers 14a and 14b from a corresponding blanket second insulator layer and the pair of patterned first insulator layers 12a and 12b from a corresponding blanket first insulator layer.
As is shown in FIG. 1, the patterned first insulator layers 12a and 12b are undercut beneath the corresponding patterned second insulator layers 14a and 14b, thus yielding a pair of first voids 18. As is also shown in FIG. 1, the pair of patterned photo resist layers 16a and 16b is partially delaminated from the pair of patterned second insulator layers 14a and 14b, thus yielding a pair of second voids 20 through which the exposed upper surfaces of the pair of patterned second insulator layers 14a and 14b are typically undesirably over-etched. The aperture of irregular sidewall etch profile which exhibits voids, as illustrated in FIG. 1, is typically obtained when employing a single isotropic etchant in forming the aperture through a blanket two-layer multi-layer insulator layer. When obtaining the irregular sidewall contour as illustrated in FIG. 1, the single isotropic etchant will typically have a substantially higher perpendicular and lateral etch rate for the blanket first insulator layer in comparison with the blanket second insulator layer, as well as a substantial interfacial permeability for a photo resist/insulator layer interface. Within advanced integrated circuits within which the blanket first insulator layer and the blanket second insulator layer are both formed of silicon oxide with substantially different chemical and/or physical properties, the single isotropic etchant which fulfills the two foregoing characteristics is typically, although not exclusively, a Buffered Oxide Etchant (BOE) wet chemical etchant.
Given that voids formed within apertures through blanket multi-layer insulator layers often provide functionality and reliability problems within integrated circuits within which are formed those blanket multi-layer insulator layers, it is thus an object of the present invention to provide a method for forming through a multi-layer insulator layer within an integrated circuit an aperture with a uniform void-free sidewall etch profile.
Methods and materials through which integrated circuit structures within integrated circuits may be uniformly and selectively formed are known in the art. For example, Moslehi, in U.S. Pat. No. 5,322,809 discloses a self-aligned method for uniformly and selectively forming a silicide layer of greater thickness upon a gate electrode of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) than upon a pair of source/drain electrode regions of the Metal Oxide Semiconductor Field Effect Transistor (MOSFET). In addition, Huang, in U.S. Pat. No. 5,342,798 discloses a differential oxidation method for uniformly and selectively forming silicide layers upon some source/drain electrode regions within a series of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) but not upon other source/drain electrode regions within the series of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). Finally, Koh, in U.S. Pat. No. 5,464,782 discloses a self-aligned method for uniformly and selectively forming silicide layers upon the gate electrode and source/drain electrode regions of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) in a fashion such that there is less susceptibility to bridging between the gate electrode and the source/drain electrode regions of the Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
Desirable in the art are methods for forming through multi-layer insulator layers within integrated circuits apertures with uniform void-free sidewall etch profiles. Particularly desirable in the art are methods through which apertures with uniform void-free sidewall etch profiles may be formed through multi-layer insulator layers formed of silicon oxide within integrated circuits.